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240pin fully buffered ddr2 sdram dimms based on 2gb a ver. this document is a general product description and is subj ect to change without notice . hynix electronics does not assume any responsibility for use of circuits described. no patent licenses are implied. rev 0. 0 1 / jan. 2009 1 this hynix?s fully buffered dimm is a high-bandwidth & large capacity channel solution that has a narrow host interface. hynix?s fb-dimm features novel architecture including the advanced memory buffer that isolates the ddr2 sdrams from the channel. this si ngle component located in the front side center of each dimm, acts as a repeater and buffer for all signals and commands which are exchanged between the host controller and the ddr2 sdrams including data in and output. the amb communicates with the host controller and adjacent dimms on a system board usin g an industry standard differential point to point link interface at 1.5v power. the amb also allows buffering of memory traffic to support large memory capacities. all memory control for the ddr2 sdram devices resides in the host, incl uding memory request initiation, timing, refresh, scrubbing, sparing, configuration access and powe r management. the amb interface is responsible for handling channel and memory requests to and from th e local fbdimm and for forwarding request to other fbdimms on the memory channel. features ? 240 pin fully buffered ecc dual-in-line ddr2 sdram module ? jedec standard double data rate2 synchronous drams (ddr2 sdrams) with 1.8v +/- 0.1v power supply ? all inputs and outputs are comp atible with sstl_1.8 interface ? built with 2gb ddr2 sdrams in 60ball fbga ? host interface and amb componen t industry standard compliant ? mbist ibist test functions ?8 bank architecture ? ocd (off-chip driver impedance adjustment) ?odt (on-die termination) ? fully differential clock operations (ck & ck) ? programmable burst length 4 / 8 with both sequential and interleave mode ? auto refresh and self refresh supported ? 8192 refresh cycles / 64ms ? serial presence detect with eeprom ? 133.35 x 30.35 mm form factor ?rohs compliant ? full dimm heat spreader ordering information note: *: fdhs means full dimm heat spreader. part name density organization # of drams # of ranks h. s type materials hmp31gf7afr4c-y5xx/sxxx 8gb 1gx72 36 2 fdhs** halogen free
rev 0.01 / jan. 2009 2 1 240pin fully buffered ddr2 sdram dimms amb information speed grade & key parameters address table supply voltages (nominal) id manufacturer revision available note d3 idt c1 now d5 idt c1 now speed grade y5 s5/6 unit ddr2 dram speed grade ddr2 667 5-5-5 ddr2 800 5-5-5 / 6-6-6 fb-dimm speed grade pc2 5300 pc2 6400 fb-dimm peak channel throughput 8.0 9.6 gbyte/s fb-dimm link transfer rate 4.0 4.8 gt/s density organization ranks sdrams # of drams # of row/bank/column address refresh method 8gb 1g x 72 2 512mb x 4 36 15(a0~a14)/3(ba0~ba2)/ 11(a0~a9,a11) 8k / 64ms min. typ max supply voltages 1.7 1.8 1.9 (dram v dd /v dd , amb v ddq ) 1.455 1.5 1.575 (amb v cc , v ccfbd ) 0.48 v dd 0.5 v dd 0.52 v dd (dram interface v tt ) this supply should track as 0.5 * 1.8 volt supply 3.0 3.3 3.6 (v ddspd )
rev 0.01 / jan. 2009 3 1 240pin fully buffered ddr2 sdram dimms input/output functional description pin name type polarity function description count sck input positive system clock input 1 sck input negative system clock input 1 pn[13:0] output positive primary northbound data 14 pn [13:0] output negative primary northbound data 14 ps[9:0] input positive primary southbound data 10 ps [9:0] input negative primary southbound data 10 sn[13:0] output positive secondary northbound data 14 sn [13:0] output negative secondary northbound data 14 ss[9:0] input positive secondary southbound data 10 ss [9:0] input negative secondary southbound data 10 scl input - serial presence detect (spd) clock input 1 sda input / output - spd data input / output 1 sa[2:0] input - spd address inputs, also used to select the dimm number in the amb 3 vid[1:0] input - voltage id: these pins must be unconnected for ddr2-based fully buff- ered dimms 2 reset input active low amb reset signal 1 rfu - - reserved for future use 16 vcc supply +1.5v amb core power and am b channel interface power(1.5volt) 8 vdd supply +1.8v dram power and amb dram i/o power 24 vtt supply +0.9v dram address/command/clock termination power(vdd/2) 4 vddspd supply +3.3v spd power 1 vss supply ground 80 dnu/m_test - / analog - / 0.9v the dnu/m_test pin provides an external connection on r/cs a-d for testing the margin of vref which is produced by a voltage divider on the module. it is not intended to be us ed in normal system operation and must not be connected(dnu) in a system. this test pin may have other features on future card designs and if it does, will be included in this specification at that time. 1 to t a l 2 40
rev 0.01 / jan. 2009 4 1 240pin fully buffered ddr2 sdram dimms pin assignment nc= no connect, rfu= reserved for future use. note: *: these pin positions are reserved for forwarded cloc ks to be used in future module implementations **: these pin positions are reserved for future architecture flexibility 1) the following signals are crc bits and t hus appear out of the normal sequence: pn12/ pn12 , sn12 / sn12 , pn13 / pn13 , sn13 / sn13 ,ps9 / ps9 , ss9 / ss9 pin name pin name pin name pin name pin name pin name 1 vdd 41 pn13 81 vss 121 vdd 161 sn13 201 vss 2 vdd 42 vss 82 ps4 122 vdd 162 vss 202 ss4 3 vdd 43 vss 83 ps4 123 vdd 163 vss 203 ss4 4 vss 44 rfu* 84 vss 124 vss 164 rfu* 204 vss 5 vdd 45 rfu* 85 vss 125 vdd 165 rfu* 205 vss 6 vdd 46 vss 86 rfu* 126 vdd 166 vss 206 rfu* 7 vdd 47 vss 87 rfu* 127 vdd 167 vss 207 rfu* 8 vss 48 pn12 88 vss 128 vss 168 sn12 208 vss 9 vcc 49 pn12 89 vss 129 vcc 169 sn12 209 vss 10 vcc 50 vss 90 ps9 130 vcc 170 vss 210 ss9 11 vss 51 pn6 91 ps9 131 vss 171 sn6 211 ss9 12 vtt 52 pn6 92 vss 132 vcc 172 sn6 212 vss 13 vcc 53 vss 93 ps5 133 vcc 173 vss 213 ss5 14 vss 54 pn7 94 ps5 134 vss 174 sn7 214 ss5 15 vtt 55 pn7 95 vss 135 vtt 175 sn7 215 vss 16 vid1 56 vss 96 ps6 136 vid0 176 vss 216 ss6 17 reset 57 pn8 97 ps6 137 dnu/m_test 177 sn8 217 ss6 18 vss 58 pn8 98 vss 138 vss 178 sn8 218 vss 19 rfu** 59 vss 99 ps7 139 rfu** 179 vss 219 ss7 20 rfu** 60 pn9 100 ps7 140 rfu** 180 sn9 220 ss7 21 vss 61 pn9 101 vss 141 vss 181 sn9 221 vss 22 pn0 62 vss 102 ps8 142 sn0 182 vss 222 ss8 23 pn0 63 pn10 103 ps8 143 sn0 183sn10223 ss8 24 vss 64 pn10 104 vss 144 vss 184 sn10 224 vss 25 pn1 65 vss 105 rfu** 145 sn1 185 vss 225 rfu* 26 pn1 66 pn11 106 rfu** 146 sn1 186 sn11 226 rfu* 27 vss 67 pn11 107 vss 147 vss 187 sn11 227 vss 28 pn2 68 vss 108 vdd 148 sn2 188 vss 228 sck 29 pn2 key 109 vdd 149 sn2 key 229 sck 30 vss 69 vss 110 vss 150 vss 189 vss 230 vss 31 pn3 70 ps0 111 vdd 151 sn3 190 ss0 231 vdd 32 pn3 71 ps0 112 vdd 152 sn3 191 ss0 232 vdd 33 vss 72 vss 113 vdd 153 vss 192 vss 233 vdd 34 pn4 73 ps1 114 vss 154 sn4 193 ss1 234 vss 35 pn4 74 ps1 115 vdd 155 sn4 194 ss1 235 vdd 36 vss 75 vss 116 vdd 156 vss 195 vss 236 vdd 37 pn5 76 ps2 117 vtt 157 sn5 196 ss2 237 vtt 38 pn5 77 ps2 118 sa2 158 sn5 197 ss2 238 vddspd 39 vss 78 vss 119 sda 159 vss 198 vss 239 sa0 40 pn13 79 ps3 120 scl 160 sn13 199 ss3 240 sa1 80 ps3 200 ss3
rev 0.01 / jan. 2009 5 1 240pin fully buffered ddr2 sdram dimms functional block diagram 8gb(1gbx72) ecc fb-dimm: hmp31gf7afr4c notes : 1. dq-to-i/o wiring may be changed within a byte. 2. there are two physical copies of each address/command/control/clock. /s0 vss d0 dqs /cs dm dq0 dq1 dq2 dq3 /dqs0 /d q s dqs0 d1 dqs /cs dm /d q s d2 dqs /cs dm dq16 dq17 dq18 dq19 /d q s d3 dqs /cs dm /d q s d4 dqs /cs dm /d q s d5 dqs /cs dm /d q s d6 dqs /cs dm /d q s d7 dqs /cs dm /d q s d8 dqs /cs dm cb0 cb1 cb2 cb3 /d q s d18 dqs /cs dm /d q s d19 dqs /cs dm /d q s d20 dqs /cs dm /d q s d21 dqs /cs dm /d q s d22 dqs /cs dm /d q s d23 dqs /cs dm /d q s d24 dqs /cs dm /d q s d25 dqs /cs dm /d q s d26 dqs /cs dm /d q s dq 8 dq9 dq10 dq11 dq24 dq25 dq26 dq27 dq 32 dq 33 dq 34 dq 35 dq40 dq41 dq42 dq43 dq48 dq49 dq50 dq51 dq56 dq57 dq58 dq59 vdd spd vdd vref vss serial pd,amb do-d35, amb do-d35 do-d35, spd, amb vcc amb vtt terminators all address/command/control/clock v tt d9 dqs /cs dm dq4 dq5 dq6 dq7 /dqs9 /d q s dqs9 d10 dqs /cs dm /dqs10 /d q s dqs11 d11 dqs /cs dm dq36 dq37 dq38 dq39 /dqs12 /d q s dqs13 d12 dqs /cs dm /dqs14 /d q s dqs14 d13 dqs /cs dm /dqs15 /d q s dqs15 d14 dqs /cs dm /dqs16 /d q s dqs16 d15 dqs /cs dm dqs17 /d q s dqs17 d16 dqs /cs dm /dqs18 /d q s dqs18 d17 dqs /cs dm cb4 cb5 cb6 cb7 /dqs17 /d q s dqs17 d27 dqs /cs dm /d q s d28 dqs /cs dm /d q s d29 dqs /cs dm /d q s d30 dqs /cs dm /d q s d31 dqs /cs dm /d q s d32 dqs /cs dm /d q s d33 dqs /cs dm /d q s d34 dqs /cs dm /d q s d35 dqs /cs dm /d q s dq20 dq21 dq23 dq44 dq45 dq46 dq47 dq52 dq53 dq54 dq55 dq60 dq61 dq62 dq63 dq64 dq65 dq66 dq67 dq60 dq61 dq62 dq63 /s1 dq22 /dqs1 dqs1 /dqs2 dqs2 /dqs3 dqs3 /dqs4 dqs4 /dqs5 dqs5 /dqs6 dqs6 /dqs7 dqs7 /dqs8 dqs8 sa0 sa1 sa2 wp scl sda a0 a1 a2 serial pd scl u0 sda i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 pn0-pn13 sn0-sn13 /pn0-/pn13 /sn0-/sn13 ps0-ps9 ss0-ss9 /ps0-/ps9 /ss0-/ss9 dq0-dq63 /s0-/cs (all sdrams) cb0-cb7 cke0 -> cke (all sdrams) dqs0-dqs17 /dqs0-/dqs17 odt -> odt (all sdrams) scl sda ba0-ba2 (all sdrams) sa0-sa2 a0-a15 (all sdrams) /reset /ras (all sdrams) /cas (all sdrams) /we (all sdrams) ck, /ck (all sdrams) sck, /sck a m b
rev 0.01 / jan. 2009 6 1 240pin fully buffered ddr2 sdram dimms architecture advanced memory buffer pin description pin name pin description count fb-dimm channel signals 99 sck system clock input, positive line 1 sck system clock input, negative line 1 pn[13:0] primary northbound data, positive lines 14 pn [13:0] primary northbound data, negative lines 14 ps[9:0] primary southbound data, positive lines 10 ps [9:0] primary southbound data, negative lines 10 sn[13:0] secondary northbound data, positive lines 14 sn [13:0] secondary northbound data, negative lines 14 ss[9:0] secondary southbound data, positive lines 10 ss [9:0] secondary southbound data, negative lines 10 fbdres to an external precision cali bration resistor connected to vcc 1 ddr2 interface signals 175 dqs[8:0] data strobes, positive lines 9 dqs [8:0] data strobes, negative lines 9 dqs[17:9]/dm[8:0] data strobes(x4 dram only), positive lines . these signals are driven low to x8 dram on writes. 9 dqs [17:9] data strobes(x4 dram only), negative lines 9 dq[63:0] data 64 cb[7:0] checkbits 8 a[15:0]a,a[15:0]b addresses. a10 is part of the pre-charge command 32 ba[2:0]a,ba[2:0]b bank addresses 6 ras a,ras b part of command, with cas , we and cs [1:0] 2 cas a,cas b part of command, with ras , we and cs [1:0] 2 we a,we b part of command, with ras , we and cs [1:0] 2 odta,odtb on-die termination enable 2 cke[1:0]a,cke[1:0]b clock enable(one per rank) 4 cs[1:0]a,cs[1:0]b chip select(one per rank) 4 clk[3:0] clk[1:0] used on 9 and 18 device dimms, clk[3:0] used on 36 device dimms. clk[3:2] should be output disabled when not in use. 4 clk [3:0] negative lines for clk[3:0] 4 ddrc_c14 ddr compensation: common return pin for ddrc_b18 and ddrc_c18 1 ddrc_b18 ddr compensation: resistor connected to common return pin ddrc_c14 1 ddrc_c18 ddr compensation: resistor connected to common return pin ddrc_c14 1 ddrc_b12 ddr compensation: resistor connected to vss 1 ddrc_c12 ddr compensation: resistor connected to vdd 1
rev 0.01 / jan. 2009 7 1 240pin fully buffered ddr2 sdram dimms advanced memory buffer pin description note: 1. system clock signals sck and sck switch at one half the dram ck/ ck frequency. 2. testlo_ab20 and testlo_ac20 should be configured for debug purposes on protype dimms: each pin should have a zero ohm resistor pulldown to ground, and an unpopulated resi stor pullup to vcc. these resistors can be replaced on production dimms with a direct connection to ground. pin name pin description count spd bus interface signals 5 scl serial presence detect (spd) clock input 1 sda spd data input / output 1 sa{2:0] spd address inputs, also used to select the dimm number in the amb 3 miscellaneous signals 163 plltsto pll clock observability output 1 vccapll analog vcc for the pll. tied with low pass filter to vcc. 1 vssapll analog vss for the pll. tied to 1 test_pin# leave floating on the dimm 6 testlo_pin# tie to ground on the dimm 2 5 bfunc tie to ground to set functionality as ?buffer on dimm.? 1 reset amb reset signal 1 nc no connect. many nc are connected to vdd on the dimm, to lower the impedance of the vdd power islands. 129 rfu reserved for future use 18 power/ground signals 213 v cc amb core power(1.5 volt) 24 v ccfbd amb channel i/o power(1.5 volt) 8 v dd amb dram i/o power (1.8 volt) 24 v ddspd spd power (3.3 volt) 1 v ss ground 156 total 655
rev 0.01 / jan. 2009 8 1 240pin fully buffered ddr2 sdram dimms pin assignments for the advanced memory buffer(am b) (top view) 655-ball lfbga 0.8 mm x 0.8 mm pitch left side nc= no connect, rfu= reserved for future use. note: a. these pin positions are reserved for forwarded cl ocks to be used in future amb implementations 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 a vss dq26 dq12 vdd dqs10 dq13 vdd dqs1 dq10 vdd test vdd vdd b vdd dqs3 dqs 3vss dq14dqs 10 vss dq11 dqs1 vss ddrc testlo vdd vss c vss dqs2 dq18 vss dq4 dqs 9 vss dq15 dq9 vss dq8 ddrc vss ddrc dqs17 d dq19 dqs 2 vss dq16 dq24 vss dqs9 dq7 vss dq3 dqs0 vss dqs 8dqs8vdd e dq21 vss dq17 dq29 vss dq25 dq6 vss dq5 dq1 vss dq0 cb1 vss cb2 f vss dq20 dq23 vss dq31 dq27 vss testlo test vss dqs 0dq2 vdd cb0cb3 gdqs 11 dqs11 nc nc nc vss dqs12 dqs 12 nc nc nc bfunc rfu rfu rfu h dq22 vss nc nc nc dq28 dq30 vss nc nc nc vss vdd vss vdd j vss clk2 nc nc nc ba1a vss cke1a nc nc nc vdd vss vdd vss kclk 2clk0 nc nc nc vss we aras a nc nc nc vss vcc vss vcc lclk 0 vss nc nc nc a0a cke0a vss nc nc nc vcc vss vcc vss modt0arfu nc nc nc cas a vss ba2a nc nc nc vss vcc vss vcc ncs 1a cs 0a nc nc nc vss ba0a a10a nc nc nc vcc vss vcc vss p a6a vss nc nc nc a2a a1a a3a nc nc nc vss vcc vss vcc r vss a8a nc nc nc a11a vss a5a nc nc nc vcc vss vcc vss t a4a a13a nc nc nc vss a9a a7a nc nc nc vss vcc vss vcc upn0pn 0 nc nc nc a15a a14a a12a nc nc nc rfu vccfbd vss vss vpn1pn 1vsssn0sn 0 vccfbd vss vccfbd vss rfu a rfu a vccfbd vss vss vss wpn2pn 2vsssn1sn 1sn 3sn 4sn 5sn 13 sn 12 sn 6sn 7sn 8sn 9sn 10 ypn3pn 3vsssn2sn 0 sn3 sn4 sn6 sn13 sn12 sn6 sn7 sn8 sn9 sn10 aa vss pn4 pn 4 vss vss vss vss vss vss vss vss vss vss vss vss ab vss reset pn 5pn 13 rfu a pn 12 pn 6pn 7pn 8pn 9vssapllvccapllpn 10 pn 11 ac vss pn5 pn13 rfu a pn12 pn6 pn7 pn8 pn9 fbdres plltsto pn10 pn11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
rev 0.01 / jan. 2009 9 1 240pin fully buffered ddr2 sdram dimms right side nc= no connect, rfu= reserved for future use. note: a. these pin positions are reserved for forwarded cl ocks to be used in future amb implementations 16 17 18 19 20 21 22 23 24 25 26 27 28 29 a vdd test vdd dq52 dqs15 vdd dq49 dqs 6 vdd dq48 dq38 vdd b vdd test ddrc vss dqs 15 dq53 vss dqs6 dq50 vss dqs 13 dqs13 vss cdqs 17 vss ddrc dq54 vss dq55 dq51 vss dqs7 dq56 vss dq46 dqs 14 vdd d cb6 cb7 vss dqs16 dq63 vss dq59 dqs 7 vss dq36 dq44 vss dqs14 dq47 evsscb5dqs 16 vss dq61 dq57 vss dq58 dq39 vss dq33 dq45 vss dq41 f cb4 vdd dq62 dq60 vss test test vss dq37 dq35 vss dqs 5dq43 vss gtestlorfurfuncncncdqs4dqs 4 vss nc nc nc dqs5 dq40 h vss vdd vss nc nc nc vss dq34 dq32 nc nc nc vss dq42 j vdd vss vdd nc nc nc ras bvss rfu nc nc nc clk 3vss k vss vcc vss nc nc nc odt0b cs 1b vss nc nc nc clk 1clk3 l vcc vss vcc nc nc nc vss cas bwe bnc nc nc vssclk1 m vss vcc vss nc nc nc cs 0b vss ba1b nc nc nc cke0b vss n vcc vss vcc nc nc nc a0b a2b vss nc nc nc ba0b ba2b p vss vcc vss nc nc nc vss a4b a1b nc nc nc vss cke1b r vcc vss vcc nc nc nc a6b vss a10b nc nc nc a3b vss t vss vcc vss nc nc nc a11b a9b vss nc nc nc a7b a5b u vss vccfbd rfu nc nc nc a8b a15b a14b sa0 scl sda ps 8ps8 v vccfbd vss vccfbd vss vccfbd rfu a rfu a vss a13b a12b sa2 sa1 ps 7ps7 w vss ss 0ss 1ss 2ss 3ss 4ss 9ss 5ss 6ss 7ss 8vssps 6ps6 y vss ss0 ss1 ss2 ss3 ss4 ss9 ss5 ss6 ss7 ss8 vss ps 5ps5 aa vss vss vss vss vss vss vss vss vss vss vss ps 9ps9vss ab vss sn 11 vss sck testlo ps 0ps 1ps 2ps 3ps4rfu a vddspd vss ac rfu sn11 vss sck testlops0ps1ps2ps3ps4rfu a vss 16 17 18 19 20 21 22 23 24 25 26 27 28 29
rev 0.01 / jan. 2009 10 1 240pin fully buffered ddr2 sdram dimms advanced memory buffer(amb) dram interface specifications please refer to the amb specificat ion for all technical requirements the following specifications for the amb constitute the subset which is critical for proper operation of the ddr2 sdram interface. note: this list is not complete, more information will follow in later revisions of this specification. critical amb specifications note 1: the timing numbers are for example only. design shou ld be based on the latest component specifications symbol parameter type vddq =1.8v +/-0.1v units notes min. max tsu dq to dqs / dqs setup time (read) input 245 ps 1 th dq to dqs / dqs hold time (read) input 245 ps 1 tdvbamb amb data valid before dqs output 470 ps 1 tdvaamb amb data valid after dqs output 470 ps 1 tcvbamb c/a/cntl valid before clock output 1030 ps 1 tcvaamb c/a/cntl valid after clock output 890 ps 1 tdqsckamb dqs/dqs -to-ck/ck output skew output -240 240 ps 1 c in input capacitance(dq/dqs/dqs )2.02.5pf1
rev 0.01 / jan. 2009 11 1 240pin fully buffered ddr2 sdram dimms basic functionality 1. advanced memory buffer overview the advanced memory buffer reference design comp lies with the jedec fb-dimm architecture and proto- col specification. 2. advanced memory buffer functionality 2.1 advanced memory buffer ? supports channel initialization procedures as define d in the initialization chapter of the fb-dimm archi- tecture and protocol specification to align the clocks and the frame boundaries verify channel connec- tivity and identify amb dimm position. ? supports the forwarding of southbound and northbo und frames, servicing requests directed to dimm, as defined in the protocol chapter, and mergin g the return data into the northbound frames. ? if the amb resides on the last dimm in the ch annel, the amb initializes northbound frames. ? detects errors on the channel and reports them to the host memory controller. ? acts as dram memory buffer for all read, write and configuration accesses addressed to the dimm. ? provides a read buffer fifo and a write buffer fifo. ? supports an smbus protocol interface for access to the amb configuration registers. ? provides logic to support membist an d ibist design for test functions. ? provides a register interface for the thermal sensor and status indicator. ? functions as a repeater to extend the maximum length of fbd links. 2.2 transparent mode for dram test support in this mode, the advanced memory buffer will provid e lower speed tester access to dram pins through the fb-dimm i/o pins. this allows the tester to send and arbitrary test pattern to the drams. transparent mode only supports a maximum dram frequency equivalent to ddr2 400. transparent mode functionality: ? reconfigure fb-dimm inputs from differential high speed link receivers to two single ended lower speed receivers(~200 mhz) ? these inputs directly control ddr2 command/address and input data that is replicated to all drams ? used low speed direct drive fb-dimm outputs to bypass high speed parallel/serial circuitry and provide test results back to tester 2.3 ddr2 sdram ? supports ddr2 at speeds of 533,667 and 800 mt/s ? supports 2gb devices in x4 configurations ? 72 bit ddr2 sdram memory array
rev 0.01 / jan. 2009 12 1 240pin fully buffered ddr2 sdram dimms 3. advanced memory buffer block diagram piso re-synch demux re-time data merge data merge re-synch demux piso re-time link init sm & control & csrs failover ibist - rx lai logic ibist - rx mux init patterns mux mux 36 deep write data fifo ddr state controller & csrs command decoder & crc check external membist ddr calibration & ddr iobist/dfx failover mux data crc gen & read fifo sync & idle pattern generator ibist - tx ibist - rx nb lai buffer link init sm & control & csrs core control & csrs thermal sensor lai controller smbus controller smbus reset control reset# pll 1x2 i0*12 i0*12 14*6*2 14*12 data in data out data out ddr io s dramclock dramclock# dram address /commandcopy1 dram address /commandcopy2 dram address data/strobe north south northbound dataout southbound datain 14x2 dram command 14x2 10x2 10x2 advanced memory buffer block diagram
rev 0.01 / jan. 2009 13 1 240pin fully buffered ddr2 sdram dimms 4. interfaces below figure illustrates the amb and all of its inte rfaces.they consists of two fb-dimm links, one ddr2 channel and an smbus interface. each fb-dimm link co nnects the amb to a host memory controller or an adjacent fb-dimm. the ddr2 cha nnel supports direct connection to the ddr2 sdrams on a fully buffered dimm. 4.1 fbd high-speed differential point -to-point link (at 1.5v) interfaces the advanced memory buffer supports one fbd channe l consisting of two bidirectional link interfaces using high speed differential poin t-to-point electrical signaling. the southbound input link is 10 la nes wid and carries commands and wr ite data from the host memory controller or the adjacent dimm in the host direction. the southbound output link forwards this same data to the next fbd. the northbound input link is 13 to 14 lanes wide and ca rries read return data or status information from the next fb-dimm in the chain back towards the host. the northbound output link forwards this informa- tion back towards the host and multiplexes in any read return data or status info rmation that is generated internally. 4.2 ddr2 channel the ddr2 channel on the advanced memory buffer supports direct connection to ddr2 sdrams. the ddr2 channel supports two ranks of eight banks with 16 row/column request, 64 data signals, and eight check-bit signals. there are two copies of address an d command signals to support dimm routing and electrical require- ments. four transfer bursts are driven on the data and check-bit lines at 800 mhz. propagation delays between read data/check-bit strobe lanes on a given channel can differ. each strobe can be calibrated by hardware state machines using write/read trial and error. hardware aligns the read data and check-bits to a single core clock. the advanced memory buffer pr ovides four copies of the command clock phase refer- ences(clk[3:0]) and write data/check-bit strobes(dqss) for each dram nibble. amb smbus memory interface ddr2 channel nb fbd in link sb fbd out link nb fbd out link sb fbd in link primary or host direction secondary or to optional next fbd advanced memory buffer interfaces
rev 0.01 / jan. 2009 14 1 240pin fully buffered ddr2 sdram dimms 4.3 smbus slave interface the advanced memory buffer supports an smbus interf ace to allow system access to configuration regis- ters independent of the fb-dimm link. the advanced memory buffer will never be a master on the smbus, only a slave. serial smbus data tr ansfer is supported at 100 khz. smbu s access to the advanced memory buffer may be a requirement to boot and to set link strength, frequency and ot her parameters needed to insure robust configurations. it is also required fo r diagnostic support when the link is down. the smbus address straps located on the dimm connector are used by the unique id. 4.4 fbd channel latency fb-dimm channel latency is measured from the time a read request is driven on the fb-dimm channel pins to the time when the first 16 bytes (2nd chunk) of re ad completion data is sampled by the memory con- troller. when not using the variable read latency capa bility, the latency for a specific dimm on a channel is always equal to the latency for any other dimm on that channel. however, the latency for each dimm in a specific configuration with some number of dimms in stalled. as more dimms ar e added to the channel, additional latency is required to read from each di mm on the channel. becaus e the channel is based on the point to point interconnection of buffer componen ts between dimms, memory requests are required to travel through n-1 buffers before reaching the nth buffer. the result is that a 4 dimm channel configura- tion will have greater idle read latency compared to a 1dimm channel configuration. the variable read latency capability can be used to redu ce latency for dimms closer to the host. the idle latencies listed in this section are representative of what might be achi eved in typical amb design s. actual implementations with latencies less than the values listed will ha ve higher application performance and vice versa. 4.5 peak theoretical throughput an fb-dimm channel transfers read comp letion data on the fbd northbound da ta connection. 144 bits of data are transferred for every fbd northbound data frame. this matc hes the 18-byte data transfer of an ecc ddr dram in a single dram command clock. a dram burst of 8 from a single channel or a dram burst of four from two lock stepped channels provides a tota l of 72 bytes of data(64 bytes plus 8 bytes ecc) the fbd frame rate matches the dram command clock because of the fixed 6:1 ratio of the fbd channel clock to the dram command clock. therefore, the nort hbound data connection will exhibit the same peak theoretical throughput as a single dram channel. for example, when using ddr2 533 drams, the peak theoretical throughput as a single dram channel.for example, when using ddr2 533 drams, the peak theoretical bandwidt h of the northbound data connection is 4.276 gb/sec. write data is transferred on the fbd southbound comma nd and data connection, via command+wdata frames. 72 bits of data are transferred for every fbd command+wda ta frame. two command+wdata frames match the 18-byte data transfer of and ecc ddr dram in a single dram co mmand clock. a dram burst of 8 transfers from a single channel, or a burst of 4 from two lock-step channels prov ides a total of 72 bytes of da ta(64 bytes plus & bytes ecc) when the fbd frame rate matches the dram command cloc k, the southbound command and data connection will exhibit one half the peak theoretical throughput of a single dram channel. for example, when using ddr2 533 drams, the peak theoretical bandwi dth of the southbound command and data connection is 2.133 gb/sec. the total peak theoretical throughput for a single fbd cha nnel is defined as the sum of the peak theoretical through- put of the northbound data connection and the southbound command and data connection. when the fbd frame rate matches the dram command clock, this is equal to 1.5 time s the peak theoretical throughp ut of a single dram chan- nel. for example, when using ddr2 533 drams, the peak theoretical throughput of a ddr2 533 channel would be 4.267 gb/sec, while the peak theoretical throughput of and fbd-=533 channel would be 6.4 gb/sec.
rev 0.01 / jan. 2009 15 1 240pin fully buffered ddr2 sdram dimms 5 hot-add the fb-dimm channel does not provide a mechanism to automatically detect and report the addition of a new dimm south of the currently active last dimm. it is assumed the system will be notified through some means of the addition of one or more new dimms so that specific commands can be sent to the host con- troller to initialize the newly added dimm(s) and perf orm a hot-add reset to bring them into the channel timing domain. it should be noted that the power to the dimm socket must be removed before a ?hot-add? dimm is inserted or removed. applying or removing the power to a dimm socket is a system platform function. 6 hot-remove in order to accomplish removal of dimms the host mu st perform a fast reset sequence targeted at the data dimm that will be retained on the channel. the fast reset re-establish the appropriate last dimm so that the southbound tx outputs of the last dimm and the southbound and northbound outputs of the dimms beyond the last active dimm are disabled. on ce the appropriate outputs are disabled the system can coordinate the procedure to remove power in prep aration for physical removal of the dimm if needed. it should be noted that the power to the dimm so cket must be removed before a ?hot-add? dimm is inserted or removed. applying or removing the power to a dimm socket is a system platform function. 7 hot-replace hot replace of dimm is accomplished through combing the hot-remove and hot-add process.
rev 0.01 / jan. 2009 16 1 240pin fully buffered ddr2 sdram dimms electrical characteristics absolute maximum ratings note: 1. stress greater than those listed may cause permanent dama ge to the device. this is a stress rating only, and device functional operation at or above the conditions indicate d is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. operating temperature range note: 1. within the dram component case temperature range all dram specification will be supported. 2. if the dram case temperature is above 85 o c, the auto-refresh command in terval has to be reduced to trefi =3.9us. supply voltage levels and dc operating conditions. note: 1. applies for smb and spd bus signals. 2. applies for amb cmos signal reset. 3. for all other amb related dc parameters, please refer to the high speed differential link interface specifications parameter symbol value unit note voltage on any pins relative to vss v in ,v out - 0.3 v ~ 1.75 v v 1 voltage on v cc relative to vss v cc - 0.3 v ~ 1.75 v v 1 voltage on v dd relative to vss v dd - 0.5 v ~ 2.3 v v 1 voltage on v tt relative to vss v tt - 0.5 v ~ 2.3 v v 1 storage temperature range t stg - 55 o c ~ 100 o c o c 1 parameter symbol rating units notes amb component case temperature range t case 0 ~ + 110 o c dram component case temperature range t case 0 ~ + 95 o c1,2 parameter symbol min nom max unit note amb supply voltage v cc 1.4 1.5 1.6 v dram supply voltage v dd 1.7 1.8 1.9 v termination voltage v tt 0.48 v dd 0.50 v dd 0.52 v dd v eeprom supply voltage v ddspd 1.7 3.3 3.6 v dc input logic high(spd) v ih (dc) 0.7*v ddspd -v ddspd + 0.5 v 1 dc input logic low(spd) v il (dc) - 0.6 - 0.5 v ddspd v1 dc input logic high(reset) v ih (dc) 0.7*v ddspd -v ddspd + 0.5 v 2 dc input logic low(reset) v il (dc) 1.0 - - v 2 leakage current (reset) il -90 - +90 ua 2 leakage current (link) il -5 - +5 ua 3
rev 0.01 / jan. 2009 17 1 240pin fully buffered ddr2 sdram dimms timing parameters note : 1. defined in fb-dimm archit ecture and protocol spec. environmental parameters note : 1. the designer must meet the case temperature specifications for individual module components. 2. stresses greater than those listed may cause permanent da mage to the device. this is a stress rating only, and device functional operation at or above the conditions indi cated is not implied. exposure to absolute maximum rating conditions for extended periods parameter symbol min typ max unit note ei assertion pass-thru timing tei propagad - 4 clks - ei desertion pass-thru timing teid bitlock clks - ei assertion duration tei 100 clks 1 bit lock interval tbitlock 119 frames 1 frame lock interval tframelock 154 frames 1 symbol parameter rating units notes t opr operating temperature see note 1 h opr operating humidity(relative) 10 to 90 % 2 t stg storage temperature -50 to +100 o c 2 h stg storage humidity(without condensation) 5 to 95 % 2 p bar barometric pressure(operating) 3050 m 2 p bar barometric pressure (storage) 15240 m 2
rev 0.01 / jan. 2009 18 1 240pin fully buffered ddr2 sdram dimms idd specification and conditions i dd meauarement conditions symbol conditions idle_0 idle current, single or last dimml0 state, idle (0 bw)primary channel enabled, sec- ondary channel disabledck e high. command and address lines stable.dram clock active. idle_1 idle current, first dimml0 state, idle (0 bw)primary and secondary channels enabledcke high. command and address lines stable. dram clock active. idle_2 idle current, dram power downl0 state, idle (0 bw)primary and secondary chan- nels enabledcke low. command and addre ss lines floated.dram clock active, odt and cke driven low. active_1 active powerl0 state.50% dram bw, 67% read, 33% write.primary and secondary channels enabled. dram clock active, cke high. active_2 active power, data pass throughl0 stat e.50% dram bw to downstream dimm, 67% read, 33% write.primary and secondary channels enabledcke high. command and address lines stable.dram clock active. l0s channel standby average power over 42 frames where the channel enters and exits l0sdrams idle (0 bw).cke low. command and address lines floated.dram clocks active, ode and cke driven low. training (for amb spec, not in spd) training primary and secondary channels enabled.100% toggle on all channels lanes.drams idle (0 bw).cke high. command and address lines stable.dram clock active.
rev 0.01 / jan. 2009 19 1 240pin fully buffered ddr2 sdram dimms idd power supply currents specifications. sac timing parameters by speed grade note: 1) assure that primary channel drive strength at 100% with de-emphasis at -6.5dbsecondary channel drive strength at 60% with de-emphasis at -3db when enabled.address an d data fields are pseudo-random, which provides a 50% toggle rate on dram data lines and link lanes when data is being transferred. assuming 1 activate command and 1 read/write command per bl=4 transferbl=4.10 lanes southbound and 14 lanes northbound are enabled and active (12 lanes nb if non-ecc dimm). spd specific assumption:number of devices on the specif ic dimm assumed.termination of command, address, and control is actual value used on the dimm .ecc or non-ecc as per the specific dimm. spd specifies delta tamb power spec specific assumpti ons:dual rank x8 ecc dimm assumed (18 dram devices present on dimm)modeled with 27 ohm termination for co mmand, address, and clocks, and 47 ohm termination for control. ecc dimm assumed (72 bit data, 14 lanes northbound). amb specification specifies current for each rail. power supply max. unit note1) icc_idle_0 @1.5v tbd ma idd_idle_0 @1.8v tbd ma idle_0 total power tbd w icc_idle_1 @1.5v tbd ma idd_idle_1 @1.8v tbd ma idle_1 total power tbd w icc_idle_2 @1.5v tbd ma idd_idle_2 @1.8v tbd ma idle_2 total power tbd w icc_active_1 @1.5v tbd ma idd_active_1 @1.8v tbd ma active_1 total power tbd w icc_active_2 @1.5v tbd ma idd_active_2 @1.8v tbd ma active_2 total power tbd w icc_l0s @1.5v tbd ma idd_l0s @1.8v tbd ma l0s total power tbd w icc_training @1.5v tbd ma idd_training @1.8v tbd ma training total power tbd w
rev 0.01 / jan. 2009 20 1 240pin fully buffered ddr2 sdram dimms termination current internal signals are terminated on the dimm through resistors to an external power supply vtt = vdd / 2.modeled with 30 ohm termination for clocks, 39 oh mfor command / address and 47 ohm for control. thevtt power supply must be able to source and sinkthese currents: vtt currents table description symbol typ max unit idle current, dram power down (conditions tbd) i tt1 -700ma active power, 50% dram bw (conditions tbd) i tt2 -700ma
rev 0.01 / jan. 2009 21 1 240pin fully buffered ddr2 sdram dimms package outline 1gbx72, 8gb module (2 ran ks of x4 based ddr2 sdrams) hmp31gf7afr4c note 1: all dimensions are typical millimet er scale unless otherwise stated. front view back view front view with heat spreader back view with heat spreader side 1.270.10 3.0 max 8.20 max 5.20 max 133.35 0.15 30.35 5.00 67.00 51.00 4.0 0.1
rev 0.01 / jan. 2009 22 1 240pin fully buffered ddr2 sdram dimms revision history revision history date remark 0.01 first version release jan. 2009

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